CLR_TXF=0, DQS_EN=0, SWRSTHD=0, CLR_RXF=0, DQS_LAT_EN=0, SWRSTSD=0, MDIS=0, DDR_EN=0
Module Configuration Register
| SWRSTSD | Software reset for Serial Flash domain 0 (0): No action 1 (1): Serial Flash domain flops are reset. Does not reset configuration registers. It is advisable to reset both the serial flash domain and AHB domain at the same time. Resetting only one domain might lead to side effects. The software resets need the clock to be running to propagate to the design. The MCR[MDIS] should therefore be set to 0 when the software reset bits are asserted. Also, before they can be deasserted again (by setting MCR[SWRSTSD] to 0), it is recommended to set the MCR[MDIS] bit to 1. Once the software resets have been deasserted, the normal operation can be started by setting the MCR[MDIS] bit to 0. |
| SWRSTHD | Software reset for AHB domain 0 (0): No action 1 (1): AHB domain flops are reset. Does not reset configuration registers. It is advisable to reset both the serial flash domain and AHB domain at the same time. Resetting only one domain might lead to side effects. The software resets need the clock to be running to propagate to the design. The MCR[MDIS] should therefore be set to 0 when the software reset bits are asserted. Also, before they can be deasserted again (by setting MCR[SWRSTHD] to 0), it is recommended to set the MCR[MDIS] bit to 1. Once the software resets have been deasserted, the normal operation can be started by setting the MCR[MDIS] bit to 0. |
| END_CFG | Defines the endianness of the QSPI module.For more details refer to Byte Ordering Endianess |
| DQS_LAT_EN | DQS Latency Enable: This field is valid when latency is included in between read access from FLash in case when QSPI_MCR[DQS_EN] is 1 0 (0): DQS Latency disabled 1 (1): DQS feature with latency included enabled |
| DQS_EN | DQS enable: This field is valid for both SDR and DDR mode 0 (0): DQS disabled. 1 (1): DQS enabled- When enabled, the incoming data is sampled on both the edges of DQS input when QSPI_MCR[DDR_EN] is set, else, on only one edge when QSPI_MCR[DDR_EN] is 0. The QSPI_SMPR[DDR_SMP] values are ignored. |
| DDR_EN | DDR mode enable: 0 (0): 2x and 4x clocks are disabled for SDR instructions only 1 (1): 2x and 4x clocks are enabled supports both SDR and DDR instruction. |
| CLR_RXF | Clear RX FIFO. Invalidate the RX Buffer. This is a self-clearing field. 0 (0): No action. 1 (1): Read and write pointers of the RX Buffer are reset to 0. QSPI_RBSR[RDBFL] is reset to 0. |
| CLR_TXF | Clear TX FIFO/Buffer. Invalidate the TX Buffer content. This is a self-clearing field. 0 (0): No action. 1 (1): Read and write pointers of the TX Buffer are reset to 0. QSPI_TBSR[TRCTR] is reset to 0. |
| MDIS | Module Disable 0 (0): Enable QuadSPI clocks. 1 (1): Allow external logic to disable QuadSPI clocks. |
| SCLKCFG | Serial Clock Configuration |